1. Field of the Invention
The present invention generally relates to semiconductor devices and fabrication methods thereof, and more particularly, to a semiconductor device having conductive bumps and a fabrication method thereof.
2. Description of Related Art
The conventional flip-chip semiconductor packaging technique is used mainly for attaching solder bumps to the corresponding solder pads formed over a chip, so as to electrically connect the chip to a chip carrier. Compared with the wire bonding technique, circuit paths formed by the flip-chip semiconductor packaging technique are shorter and have a better electrical quality. Further, the heat dissipation efficiency of the flip-chip semiconductor package can be improved in that the non-active (back) surface of the chip of the flip-chip semiconductor package is exposed to the ambience.
According to the disclosures of the U.S. Pat. Nos. 6,111,321, 6,107,180, and 6,586,323, before attaching the solder bumps on the chip by the flip-chip technique, an Under Bump Metallurgy (UBM) layer is formed on the solder pads of the chip. Thus, the solder bumps are soldered firmly onto the solder pads. However, when being electrically connected to the substrate during a reflow process and heated to a certain high temperature, the solder bumps will melt and collapse (i.e., wetting), resulting in adjacent solder bumps bridged.
Referring to FIG. 1A, a copper pillar 15 with a height of approximately 30 to 90 m is formed over a UBM layer 14 of a solder pad 11 formed over a chip 10, as disclosed in the U.S. Pat. Nos. 6,229,220, 5,656,858, 5,466,635, and 6,578,754. A solder material 16 is then applied over the copper pillar 15 to form a high standoff bump, allowing the chip 10 to be electrically connected to a chip carrier, such as a substrate. Since the melting point of copper is higher than the temperature required for the reflow process for reflowing the solder material 16, the copper pillar 15 will not collapse during reflow and thereby adjacent pillars 15 will not be bridged to cause short circuit problems.
A larger amount of thermal stress due to the mismatch of the thermal expansion coefficient between the chip and the chip career can be absorbed by the aforementioned high standoff bump when compared with the prior art. However, in the case that a larger-sized chip, such as 15×15 mm or above is used, such high standoff bumps having the copper pillar in the corner positions of the chip usually bear a greater extent of thermal stress. Thus, those corner bumps of the chip are in general unable to effectively absorb the thermal stress imposed thereto. As a result, the UBM layer tends to crack or delaminate from the solder pad attached thereto (‘C’ in FIG. 1B), as shown in FIG. 1B, thereby causing electrical performance and reliability problems.
Accordingly, how to provide a large-sized semiconductor chip having conductive bumps capable of effectively absorbing thermal stress during temperature cycle so as to prevent cracking or delamination problems from occurring has become an important issue to be resolved in the industry.